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| author | Stephen Long <steplong@quicinc.com> | 2021-05-24 18:03:46 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-05-25 16:01:44 +0100 |
| commit | a5421b54c4a333c8b3aa342cae23180d8d0ecd04 (patch) | |
| tree | 0cb9072ed74ba237b4e7fafcf6574fdb798c2664 /hw/core/machine.c | |
| parent | 74b64b2562fc9798765f2a9b883b678666b71215 (diff) | |
| download | focaccia-qemu-a5421b54c4a333c8b3aa342cae23180d8d0ecd04.tar.gz focaccia-qemu-a5421b54c4a333c8b3aa342cae23180d8d0ecd04.zip | |
target/arm: Implement SVE2 bitwise shift immediate
Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stephen Long <steplong@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-81-richard.henderson@linaro.org Message-Id: <20200430194159.24064-1-steplong@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/core/machine.c')
0 files changed, 0 insertions, 0 deletions