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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-06-23 19:04:47 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-10-14 07:10:20 -0700 |
| commit | 47c906ae6f54fa10b3f072863d8993e790a14439 (patch) | |
| tree | b76a7f6b9782e7403e4e85fa29999bfef487eefb /hw/core/numa.c | |
| parent | 68f340d4cd9f0423039e4706a6602673d7ca9101 (diff) | |
| download | focaccia-qemu-47c906ae6f54fa10b3f072863d8993e790a14439.tar.gz focaccia-qemu-47c906ae6f54fa10b3f072863d8993e790a14439.zip | |
tcg/ppc: Update vector support for VSX
The VSX instruction set instructions include double-word loads and
stores, double-word load and splat, double-word permute, and bit
select. All of which require multiple operations in the Altivec
instruction set.
Because the VSX registers map %vsr32 to %vr0, and we have no current
intention or need to use vector registers outside %vr0-%vr19, force
on the {ax,bx,cx,tx} bits within the added VSX insns so that we don't
have to otherwise modify the VR[TABC] macros.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'hw/core/numa.c')
0 files changed, 0 insertions, 0 deletions