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authorAleksandar Markovic <amarkovic@wavecomp.com>2018-08-02 16:15:52 +0200
committerAleksandar Markovic <amarkovic@wavecomp.com>2018-08-16 19:18:45 +0200
commit0413d7a55a8161ebd33541ba1df4285bf180c583 (patch)
tree34fc512e2c6b2a75bee021312435f4c5015b84b6 /hw/core/qdev-properties-system.c
parente1555d7ddf2c86fb92165e47eb092f1f5fa9e8bd (diff)
downloadfocaccia-qemu-0413d7a55a8161ebd33541ba1df4285bf180c583.tar.gz
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target/mips: Update some CP0 registers bit definitions
Update CP0 registers Config0, Config1, Config2, Config3,
Config4, and Config5 bit definitions.

Some of these bits will be utilized by upcoming nanoMIPS changes.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'hw/core/qdev-properties-system.c')
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