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authorPeter Maydell <peter.maydell@linaro.org>2017-09-07 13:54:51 +0100
committerPeter Maydell <peter.maydell@linaro.org>2017-09-07 13:54:51 +0100
commit0e1a46bbd2d6c39614b87f4e88ea305acce8a35f (patch)
treef60754bcef3ac2228d9c92eb246b8e3b4d95b70b /hw/core/qdev-properties-system.c
parentdc89a180caf143a5d596d3f2f776d13be83a687d (diff)
downloadfocaccia-qemu-0e1a46bbd2d6c39614b87f4e88ea305acce8a35f.tar.gz
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target/arm: Implement ARMv8M's PMSAv8 registers
As part of ARMv8M, we need to add support for the PMSAv8 MPU
architecture.

PMSAv8 differs from PMSAv7 both in register/data layout (for instance
using base and limit registers rather than base and size) and also in
behaviour (for example it does not have subregions); rather than
trying to wedge it into the existing PMSAv7 code and data structures,
we define separate ones.

This commit adds the data structures which hold the state for a
PMSAv8 MPU and the register interface to it.  The implementation of
the MPU behaviour will be added in a subsequent commit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-2-git-send-email-peter.maydell@linaro.org
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