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| author | Andrew Jones <ajones@ventanamicro.com> | 2024-02-15 19:39:53 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-03-08 16:32:44 +1000 |
| commit | 148189ff1313e995a0a84957c496ff92965151a2 (patch) | |
| tree | 7ce06b7b152f547420897f625d3da4822e6da7b4 /hw/core/qdev-properties-system.c | |
| parent | a0952c15556d740a8dae88c7038ad5efe68745bc (diff) | |
| download | focaccia-qemu-148189ff1313e995a0a84957c496ff92965151a2.tar.gz focaccia-qemu-148189ff1313e995a0a84957c496ff92965151a2.zip | |
target/riscv: Reset henvcfg to zero
The hypervisor should decide what it wants to enable. Zero all
configuration enable bits on reset.
Also, commit ed67d63798f2 ("target/riscv: Update CSR bits name for
svadu extension") missed one reference to 'hade'. Change it now.
Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address translation")
Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240215223955.969568-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/core/qdev-properties-system.c')
0 files changed, 0 insertions, 0 deletions