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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-03-08 00:16:27 +0000 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-03-08 00:16:27 +0000 |
| commit | cff6abd6f2fc1af588207b27f2a6b96e15bd96dc (patch) | |
| tree | 3f992bc831af100a743940049b4911e97d1ddcff /hw/core/qdev-properties.c | |
| parent | c10b02836ff02fcd09367316260f9368c5c92f28 (diff) | |
| parent | bebe80fc78cc91c4225cfb98ef3a916b9c861c60 (diff) | |
| download | focaccia-qemu-cff6abd6f2fc1af588207b27f2a6b96e15bd96dc.tar.gz focaccia-qemu-cff6abd6f2fc1af588207b27f2a6b96e15bd96dc.zip | |
Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20150303' into staging
TriCore RRR1, RRR2 instructions and bugfixes # gpg: Signature made Tue Mar 3 01:12:02 2015 GMT using RSA key ID 6B69CA14 # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" * remotes/bkoppelmann/tags/pull-tricore-20150303: target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as first opcode target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as first opcode target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as first opcode target-tricore: Add instructions of RRR2 opcode format target-tricore: fix msub32_suov return wrong results target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/core/qdev-properties.c')
0 files changed, 0 insertions, 0 deletions