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| author | Jeff Kubascik <jeff.kubascik@dornerworks.com> | 2020-01-17 14:09:31 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-01-17 14:27:16 +0000 |
| commit | ef1255212a721e3ebc2be4bec9426bda9d2ee308 (patch) | |
| tree | dc81d499d8b605c8fbc8178acd0516478c3ed56c /hw/core/qdev.c | |
| parent | 855532912b0e1bf803ae393e5b0c7e80948cd6a4 (diff) | |
| download | focaccia-qemu-ef1255212a721e3ebc2be4bec9426bda9d2ee308.tar.gz focaccia-qemu-ef1255212a721e3ebc2be4bec9426bda9d2ee308.zip | |
arm/gicv3: update virtual irq state after IAR register read
The IAR0/IAR1 register is used to acknowledge an interrupt - a read of the register activates the highest priority pending interrupt and provides its interrupt ID. Activating an interrupt can change the CPU's virtual interrupt state - this change makes sure the virtual irq state is updated. Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200113154607.97032-1-jeff.kubascik@dornerworks.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/core/qdev.c')
0 files changed, 0 insertions, 0 deletions