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| author | Stefan Hajnoczi <stefanha@redhat.com> | 2025-03-07 07:39:49 +0800 |
|---|---|---|
| committer | Stefan Hajnoczi <stefanha@redhat.com> | 2025-03-07 07:39:49 +0800 |
| commit | 98c7362b1efe651327385a25874a73e008c6549e (patch) | |
| tree | 7a4e66f22ef23113ead80db5c7e4e1601968e36a /hw/core | |
| parent | 2400fad572906127e9d453b92f90806d66583dc7 (diff) | |
| parent | 92941c94e7f4858fdd61b4c1b85f6d1c6f164359 (diff) | |
| download | focaccia-qemu-98c7362b1efe651327385a25874a73e008c6549e.tar.gz focaccia-qemu-98c7362b1efe651327385a25874a73e008c6549e.zip | |
Merge tag 'accel-cpus-20250306' of https://github.com/philmd/qemu into staging
Generic CPUs / accelerators patch queue - Merge "qemu/clang-tsa.h" within "qemu/compiler.h" - Various cleanups around accelerators initialization code (better user/system split) - Various trivial cleanups in accel/tcg/, Guard few TCG calls with tcg_enabled() - Explicit disassemble_info endianness - Improve dual-endianness support for MicroBlaze # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmfJw08ACgkQ4+MsLN6t # wN70whAAtfcdWtqseFfb6fvDtjflgxN51Ui0iaOECXUA18USKriGy34eBcMYMiM2 # +eKgU7+jI6JGE4+burcgWUsPpFFF951/A8+lyIbFgO5yToTDmC+qNe4XfmMAIyXq # uf9Obr2c0Xk9luh4odb+jPAQodw/7G1fKgcCVIJNDCl/xEcPhS9eNpTaHwcVnkWI # K6KrxWXOsqG6+evJBPWYoXtOOyt0+JcwAsJoGhprwtGm3P9+jSVXsgeGsJVyZcna # f32JtjWL754O8XeMkOn4x6rt58VrCIMKI9xT7keDyuhTCq0Zki9RO2nMU2dSw5mN # AfL9hxqUy0Nijnyslg3ugujDfTePsNyLdwwH7n0mnoD72ELi6WnhDsmOThuEB3Rd # 4/kdwTJfA/rlWk/GF1tbKW7AvQZokRARtzmL3V0HmGJu57lX+2JuszEdYBkqDEP7 # GH1I10B2yANUm+C9y3X8qWOU7Ws433ebJeJoZuyfnbZ9Me+UfRmql/oS+V8ata2i # fArEItpldUFrWRyYLkTbXrh2dgyV9yJTEir/lzOzeAZZzyabTbjf2z9qnh976GGO # 1QnDy5QA4f54kDBUZe7JK26TZsHPch7cgqXW6f8tRlJF7A9hxGK8d2TUV/lC3/vx # LUOlWNu03PhiruYmZEcWOsY3Jt9jRCF6lIryrnaJsqnVOVmMUMM= # =3TRh # -----END PGP SIGNATURE----- # gpg: Signature made Thu 06 Mar 2025 23:46:23 HKT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'accel-cpus-20250306' of https://github.com/philmd/qemu: (54 commits) include: Poison TARGET_PHYS_ADDR_SPACE_BITS definition system: Open-code qemu_init_arch_modules() using target_name() target/i386: Mark WHPX APIC region as little-endian target/alpha: Do not mix exception flags and FPCR bits target/riscv: Convert misa_mxl_max using GLib macros target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL target/xtensa: Finalize config in xtensa_register_core() target/sparc: Constify SPARCCPUClass::cpu_def target/i386: Constify X86CPUModel uses disas: Remove target_words_bigendian() call in initialize_debug_target() target/xtensa: Set disassemble_info::endian value in disas_set_info() target/sh4: Set disassemble_info::endian value in disas_set_info() target/riscv: Set disassemble_info::endian value in disas_set_info() target/ppc: Set disassemble_info::endian value in disas_set_info() target/mips: Set disassemble_info::endian value in disas_set_info() target/microblaze: Set disassemble_info::endian value in disas_set_info target/arm: Set disassemble_info::endian value in disas_set_info() target: Set disassemble_info::endian value for big-endian targets target: Set disassemble_info::endian value for little-endian targets target/mips: Fix possible MSA int overflow ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'hw/core')
| -rw-r--r-- | hw/core/cpu-common.c | 6 | ||||
| -rw-r--r-- | hw/core/cpu-system.c | 47 | ||||
| -rw-r--r-- | hw/core/cpu-user.c | 32 | ||||
| -rw-r--r-- | hw/core/generic-loader.c | 5 | ||||
| -rw-r--r-- | hw/core/meson.build | 5 |
5 files changed, 89 insertions, 6 deletions
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index cb79566cc5..d5cd227fe6 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -238,13 +238,17 @@ static void cpu_common_initfn(Object *obj) { CPUState *cpu = CPU(obj); + /* cache the cpu class for the hotpath */ + cpu->cc = CPU_GET_CLASS(cpu); + gdb_init_cpu(cpu); cpu->cpu_index = UNASSIGNED_CPU_INDEX; cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; + cpu->as = NULL; + cpu->num_ases = 0; /* user-mode doesn't have configurable SMP topology */ /* the default value is changed by qemu_init_vcpu() for system-mode */ cpu->nr_threads = 1; - cpu->cflags_next_tb = -1; /* allocate storage for thread info, initialise condition variables */ cpu->thread = g_new0(QemuThread, 1); diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index 6e307c8959..e511507e13 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -20,7 +20,11 @@ #include "qemu/osdep.h" #include "qapi/error.h" +#include "exec/address-spaces.h" +#include "exec/memory.h" #include "exec/tswap.h" +#include "hw/qdev-core.h" +#include "hw/qdev-properties.h" #include "hw/core/sysemu-cpu-ops.h" bool cpu_paging_enabled(const CPUState *cpu) @@ -147,3 +151,46 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) } return res; } + +static const Property cpu_system_props[] = { + /* + * Create a memory property for system CPU object, so users can + * wire up its memory. The default if no link is set up is to use + * the system address space. + */ + DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, + MemoryRegion *), +}; + +static bool cpu_get_start_powered_off(Object *obj, Error **errp) +{ + CPUState *cpu = CPU(obj); + return cpu->start_powered_off; +} + +static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp) +{ + CPUState *cpu = CPU(obj); + cpu->start_powered_off = value; +} + +void cpu_class_init_props(DeviceClass *dc) +{ + ObjectClass *oc = OBJECT_CLASS(dc); + + /* + * We can't use DEFINE_PROP_BOOL in the Property array for this + * property, because we want this to be settable after realize. + */ + object_class_property_add_bool(oc, "start-powered-off", + cpu_get_start_powered_off, + cpu_set_start_powered_off); + + device_class_set_props(dc, cpu_system_props); +} + +void cpu_exec_initfn(CPUState *cpu) +{ + cpu->memory = get_system_memory(); + object_ref(OBJECT(cpu->memory)); +} diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c new file mode 100644 index 0000000000..cdd8de2fef --- /dev/null +++ b/hw/core/cpu-user.c @@ -0,0 +1,32 @@ +/* + * QEMU CPU model (user specific) + * + * Copyright (c) Linaro, Ltd. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/qdev-core.h" +#include "hw/qdev-properties.h" +#include "hw/core/cpu.h" + +static const Property cpu_user_props[] = { + /* + * Create a property for the user-only object, so users can + * adjust prctl(PR_SET_UNALIGN) from the command-line. + * Has no effect if the target does not support the feature. + */ + DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState, + prctl_unalign_sigbus, false), +}; + +void cpu_class_init_props(DeviceClass *dc) +{ + device_class_set_props(dc, cpu_user_props); +} + +void cpu_exec_initfn(CPUState *cpu) +{ + /* nothing to do */ +} diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index d9f5c2e832..d3a426a1a2 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -47,11 +47,8 @@ static void generic_loader_reset(void *opaque) GenericLoaderState *s = GENERIC_LOADER(opaque); if (s->set_pc) { - CPUClass *cc = CPU_GET_CLASS(s->cpu); cpu_reset(s->cpu); - if (cc) { - cc->set_pc(s->cpu, s->addr); - } + cpu_set_pc(s->cpu, s->addr); } if (s->data_len) { diff --git a/hw/core/meson.build b/hw/core/meson.build index 65a1698ed1..b5a545a0ed 100644 --- a/hw/core/meson.build +++ b/hw/core/meson.build @@ -46,4 +46,7 @@ system_ss.add(files( 'vm-change-state-handler.c', 'clock-vmstate.c', )) -user_ss.add(files('qdev-user.c')) +user_ss.add(files( + 'cpu-user.c', + 'qdev-user.c', +)) |