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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-05-23 16:15:51 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-05-23 16:15:52 +0100 |
| commit | c9158547617584bb9d19db7fb139998fbef80133 (patch) | |
| tree | 7fd630b63555af50eaabc3101afe070345904db7 /hw/core | |
| parent | 2b5f477789aa4d0a4aa444533558e21e63a310ec (diff) | |
| parent | 1453e6627d19a8d6d54480c6980f5cef5dfc6833 (diff) | |
| download | focaccia-qemu-c9158547617584bb9d19db7fb139998fbef80133.tar.gz focaccia-qemu-c9158547617584bb9d19db7fb139998fbef80133.zip | |
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
* NMI cleanups (Bandan) * RAMBlock/Memory cleanups and fixes (Dominik, Gonglei, Fam, me) * first part of linuxboot support for fw_cfg DMA (Richard) * IOAPIC fix (Peter Xu) * iSCSI SG_IO fix (Vadim) * Various infrastructure bug fixes (Zhijian, Peter M., Stefan) * CVE fixes (Prasad) # gpg: Signature made Mon 23 May 2016 16:06:18 BST using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" * remotes/bonzini/tags/for-upstream: (24 commits) cpus: call the core nmi injection function nmi: remove x86 specific nmi handling target-i386: add a generic x86 nmi handler coccinelle: add g_assert_cmp* to macro file iscsi: pass SCSI status back for SG_IO esp: check dma length before reading scsi command(CVE-2016-4441) esp: check command buffer length before write(CVE-2016-4439) scripts/signrom.py: Check for magic in option ROMs. scripts/signrom.py: Allow option ROM checksum script to write the size header. Remove config-devices.mak on 'make clean' cpus.c: Use pthread_sigmask() rather than sigprocmask() memory: remove unnecessary masking of MemoryRegion ram_addr memory: Drop FlatRange.romd_mode memory: Remove code for mr->may_overlap exec: adjust rcu_read_lock requirement memory: drop find_ram_block() vl: change runstate only if new state is different from current state ioapic: clear remote irr bit for edge-triggered interrupts ioapic: keep RO bits for IOAPIC entry target-i386: key sfence availability on CPUID_SSE, not CPUID_SSE2 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/core')
| -rw-r--r-- | hw/core/nmi.c | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/hw/core/nmi.c b/hw/core/nmi.c index f616a79312..bfd0896daf 100644 --- a/hw/core/nmi.c +++ b/hw/core/nmi.c @@ -20,16 +20,11 @@ */ #include "qemu/osdep.h" -#include "qom/cpu.h" #include "hw/nmi.h" #include "qapi/error.h" #include "qapi/qmp/qerror.h" #include "monitor/monitor.h" -#if defined(TARGET_I386) -#include "cpu.h" -#endif - struct do_nmi_s { int cpu_index; Error *err; @@ -78,25 +73,6 @@ void nmi_monitor_handle(int cpu_index, Error **errp) } } -void inject_nmi(void) -{ -#if defined(TARGET_I386) - CPUState *cs; - - CPU_FOREACH(cs) { - X86CPU *cpu = X86_CPU(cs); - - if (!cpu->apic_state) { - cpu_interrupt(cs, CPU_INTERRUPT_NMI); - } else { - apic_deliver_nmi(cpu->apic_state); - } - } -#else - nmi_monitor_handle(0, NULL); -#endif -} - static const TypeInfo nmi_info = { .name = TYPE_NMI, .parent = TYPE_INTERFACE, |