diff options
| author | Anthony Liguori <anthony@codemonkey.ws> | 2013-08-20 11:23:52 -0500 |
|---|---|---|
| committer | Anthony Liguori <anthony@codemonkey.ws> | 2013-08-20 11:23:52 -0500 |
| commit | ecfe10c9a6f9bc77d0e4b7eb5d0f5d61e8fbaed8 (patch) | |
| tree | 7b591e576ef4fd8580bf9fc05163c5e1a2d580aa /hw/cpu/a15mpcore.c | |
| parent | 9176e8fb8f78206bd4039f001aca0d931a47d663 (diff) | |
| parent | 230058106ab26de9b876158dbe27d60719f01f51 (diff) | |
| download | focaccia-qemu-ecfe10c9a6f9bc77d0e4b7eb5d0f5d61e8fbaed8.tar.gz focaccia-qemu-ecfe10c9a6f9bc77d0e4b7eb5d0f5d61e8fbaed8.zip | |
Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20130820' into staging
target-arm queue # gpg: Signature made Tue 20 Aug 2013 08:56:28 AM CDT using RSA key ID 14360CDE # gpg: Can't check signature: public key not found # By Peter Maydell (20) and Peter Chubb (1) # Via Peter Maydell * pmaydell/tags/pull-target-arm-20130820: (21 commits) hw/timer/imx_epit: Simplify and fix imx_epit implementation default-configs: Fix A9MP and A15MP config names hw/cpu/a15mpcore: Wire generic timer outputs to GIC inputs target-arm: Implement the generic timer target-arm: Support coprocessor registers which do I/O target-arm: Allow raw_read() and raw_write() to handle 64 bit regs hw/arm/pic_cpu: Remove the now-unneeded arm_pic_init_cpu() hw/arm/xilinx_zynq: Don't use arm_pic_init_cpu() hw/arm/vexpress: Don't use arm_pic_init_cpu() hw/arm/versatilepb: Don't use arm_pic_init_cpu() hw/arm/strongarm: Don't use arm_pic_init_cpu() hw/arm/realview: Don't use arm_pic_init_cpu() hw/arm/omap*: Don't use arm_pic_init_cpu() hw/arm/musicpal: Don't use arm_pic_init_cpu() hw/arm/kzm: Don't use arm_pic_init_cpu() hw/arm/integratorcp: Don't use arm_pic_init_cpu() hw/arm/highbank: Don't use arm_pic_init_cpu() hw/arm/exynos4210: Don't use arm_pic_init_cpu() hw/arm/armv7m: Don't use arm_pic_init_cpu() target-arm: Make IRQ and FIQ gpio lines on the CPU object ... Message-id: 1377007680-4934-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
Diffstat (limited to 'hw/cpu/a15mpcore.c')
| -rw-r--r-- | hw/cpu/a15mpcore.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 4f37964434..af182da4ee 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -49,6 +49,8 @@ static int a15mp_priv_init(SysBusDevice *dev) A15MPPrivState *s = A15MPCORE_PRIV(dev); SysBusDevice *busdev; const char *gictype = "arm_gic"; + int i; + CPUState *cpu; if (kvm_irqchip_in_kernel()) { gictype = "kvm-arm-gic"; @@ -67,6 +69,22 @@ static int a15mp_priv_init(SysBusDevice *dev) /* Pass through inbound GPIO lines to the GIC */ qdev_init_gpio_in(DEVICE(dev), a15mp_priv_set_irq, s->num_irq - 32); + /* Wire the outputs from each CPU's generic timer to the + * appropriate GIC PPI inputs + */ + for (i = 0, cpu = first_cpu; i < s->num_cpu; i++, cpu = cpu->next_cpu) { + DeviceState *cpudev = DEVICE(cpu); + int ppibase = s->num_irq - 32 + i * 32; + /* physical timer; we wire it up to the non-secure timer's ID, + * since a real A15 always has TrustZone but QEMU doesn't. + */ + qdev_connect_gpio_out(cpudev, 0, + qdev_get_gpio_in(s->gic, ppibase + 30)); + /* virtual timer */ + qdev_connect_gpio_out(cpudev, 1, + qdev_get_gpio_in(s->gic, ppibase + 27)); + } + /* Memory map (addresses are offsets from PERIPHBASE): * 0x0000-0x0fff -- reserved * 0x1000-0x1fff -- GIC Distributor |