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| author | Michael Tokarev <mjt@tls.msk.ru> | 2023-11-14 19:06:48 +0300 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-11-15 11:09:17 +0300 |
| commit | 487152fa1fdb2ad25a15986d13a5dd43ae9e219f (patch) | |
| tree | 9b352a49c09a747281ec4cade5bbc8a8b0160634 /hw/cxl/cxl-component-utils.c | |
| parent | 2cf91b9ae6df17ac99dd212016e2d204cc2f6a74 (diff) | |
| download | focaccia-qemu-487152fa1fdb2ad25a15986d13a5dd43ae9e219f.tar.gz focaccia-qemu-487152fa1fdb2ad25a15986d13a5dd43ae9e219f.zip | |
hw/cxl: spelling fixes: limitaions, potentialy, intialized
Fixes: 388d6b574e28 "hw/cxl: Use switch statements for read and write of cachemem registers" Fixes: 3314efd276ad "hw/cxl/mbox: Add Physical Switch Identify command." Fixes: 004e3a93b814 "hw/cxl: Add tunneled command support to mailbox for switch cci." Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'hw/cxl/cxl-component-utils.c')
| -rw-r--r-- | hw/cxl/cxl-component-utils.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index d0245cc55d..29d477492b 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -81,7 +81,7 @@ static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr offset, return 0; default: /* - * In line with specifiction limitaions on access sizes, this + * In line with specification limitaions on access sizes, this * routine is not called with other sizes. */ g_assert_not_reached(); @@ -152,7 +152,7 @@ static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value, return; default: /* - * In line with specifiction limitaions on access sizes, this + * In line with specification limitaions on access sizes, this * routine is not called with other sizes. */ g_assert_not_reached(); |