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| author | Li Zhijian <lizhijian@fujitsu.com> | 2025-02-03 16:19:07 +0000 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2025-02-21 07:18:42 -0500 |
| commit | d3c92cf6dcab028d05f306d4d50511aa805d2385 (patch) | |
| tree | 4e93032f8fd5bcf5990dee06618d3e1a63f80286 /hw/cxl/cxl-component-utils.c | |
| parent | 06953e7e5ea5e8fa0b7b704bdb66ab1e62f1f378 (diff) | |
| download | focaccia-qemu-d3c92cf6dcab028d05f306d4d50511aa805d2385.tar.gz focaccia-qemu-d3c92cf6dcab028d05f306d4d50511aa805d2385.zip | |
hw/mem/cxl_type3: Ensure errp is set on realization failure
Simply pass the errp to its callee which will set errp if needed, to enhance error reporting for CXL Type 3 device initialization by setting the errp when realization functions fail. Previously, failing to set `errp` could result in errors being overlooked, causing the system to mistakenly treat failure scenarios as successful and potentially leading to redundant cleanup operations in ct3_exit(). Signed-off-by: Li Zhijian <lizhijian@fujitsu.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20250203161908.145406-5-Jonathan.Cameron@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/cxl/cxl-component-utils.c')
0 files changed, 0 insertions, 0 deletions