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| author | Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> | 2022-01-06 22:01:02 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-08 15:46:10 +1000 |
| commit | 6bf4bbed205127f3805e960a1213c2289db89114 (patch) | |
| tree | 0b2772863db054b3e1fe1ce754c59c08d878618d /hw/display/vhost-user-gpu.c | |
| parent | 57c108b86461a050a58b1ca9d31fd6e4af32205c (diff) | |
| download | focaccia-qemu-6bf4bbed205127f3805e960a1213c2289db89114.tar.gz focaccia-qemu-6bf4bbed205127f3805e960a1213c2289db89114.zip | |
target/riscv: support for 128-bit shift instructions
Handling shifts for 32, 64 and 128 operation length for RV128, following the general framework for handling various olens proposed by Richard. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-13-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/display/vhost-user-gpu.c')
0 files changed, 0 insertions, 0 deletions