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| author | Richard Henderson <richard.henderson@linaro.org> | 2024-08-19 17:39:55 +1000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-08-21 09:11:26 +1000 |
| commit | ded1db48c9f9b35f6d9569e53503e2b345f6d44e (patch) | |
| tree | 83fc56b4e8bd61b1e69492a9c5ecdbd946826e83 /hw/display/vhost-user-gpu.c | |
| parent | 83a3a20e59fa4b1add714bb4062af0d144b67ab7 (diff) | |
| download | focaccia-qemu-ded1db48c9f9b35f6d9569e53503e2b345f6d44e.tar.gz focaccia-qemu-ded1db48c9f9b35f6d9569e53503e2b345f6d44e.zip | |
target/i386: Fix tss access size in switch_tss_ra
The two limit_max variables represent size - 1, just like the
encoding in the GDT, thus the 'old' access was off by one.
Access the minimal size of the new tss: the complete tss contains
the iopb, which may be a larger block than the access api expects,
and irrelevant because the iopb is not accessed during the
switch itself.
Fixes: 8b131065080a ("target/i386/tcg: use X86Access for TSS access")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2511
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240819074052.207783-1-richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Diffstat (limited to 'hw/display/vhost-user-gpu.c')
0 files changed, 0 insertions, 0 deletions