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| author | Igor Kovalenko <igor.v.kovalenko@gmail.com> | 2009-07-12 12:35:31 +0400 |
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| committer | Blue Swirl <blauwirbel@gmail.com> | 2009-07-12 08:46:54 +0000 |
| commit | 5210977a8511fc0c4a8a1a68c01fa3b65e29edc0 (patch) | |
| tree | dd12f3bcc62297f325c30718c6d42764dff0afd6 /hw/eccmemctl.c | |
| parent | 49e6637386acb8824114ed10308ed7869472ec0f (diff) | |
| download | focaccia-qemu-5210977a8511fc0c4a8a1a68c01fa3b65e29edc0.tar.gz focaccia-qemu-5210977a8511fc0c4a8a1a68c01fa3b65e29edc0.zip | |
sparc64: trap handling corrections
On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote: > On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote: >> Good trap handling is required to process interrupts. >> This patch fixes the following: >> >> - sparc64 has no wim register >> - sparc64 has no psret register, use IE bit of pstate >> extract IE checking code to cpu_interrupts_enabled >> - alternate globals are not available if cpu has GL feature >> in this case bit AG of pstate is constant zero >> - write to pstate must actually write pstate >> even if cpu has GL feature >> >> Also timer interrupt is handled using do_interrupt. > > A bit too much for one patch. Please also remove the code instead of > commenting out. I now excluded timer interrupt related part. To my mind other changes are essentially tied together. > PUT_PSR for Sparc64 needs CC_OP = CC_OP_FLAGS; like Sparc32. Fixed, please find attached the updated version. -- Kind regards, Igor V. Kovalenko
Diffstat (limited to 'hw/eccmemctl.c')
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