diff options
| author | Artyom Tarasenko <atar4qemu@googlemail.com> | 2009-12-13 13:30:44 +0000 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2009-12-13 13:30:44 +0000 |
| commit | 82407d1a4035e5bfefb53ffdcb270872f813b34c (patch) | |
| tree | a3ff4483742ec33867dc4c2b944377b7fafe6903 /hw/fdc.c | |
| parent | c5de386ac9da35bf2cd7dc92893b0517f12bfc3a (diff) | |
| download | focaccia-qemu-82407d1a4035e5bfefb53ffdcb270872f813b34c.tar.gz focaccia-qemu-82407d1a4035e5bfefb53ffdcb270872f813b34c.zip | |
fdc/sparc32: don't hang on detection under OBP
Stepping through the SS-5's OBP initialization routines it looks like reading fdc main status register should clear the fd interrupt. The patch doesn't fix problems with fdc on sparc platform, it only fixes fdc detection. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw/fdc.c')
| -rw-r--r-- | hw/fdc.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/hw/fdc.c b/hw/fdc.c index e875291a3a..11ea439ed3 100644 --- a/hw/fdc.c +++ b/hw/fdc.c @@ -960,6 +960,12 @@ static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl) fdctrl->dsr &= ~FD_DSR_PWRDOWN; fdctrl->dor |= FD_DOR_nRESET; + /* Sparc mutation */ + if (fdctrl->sun4m) { + retval |= FD_MSR_DIO; + fdctrl_reset_irq(fdctrl); + }; + FLOPPY_DPRINTF("main status register: 0x%02x\n", retval); return retval; |