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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-06-14 15:59:12 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-06-14 15:59:12 +0100 |
| commit | 811595a2d4ab8c6354857a50ffd29fafce52a892 (patch) | |
| tree | a351ae57ff1c04d5b136c9f3deef1727ad4c9b05 /hw/gpio/omap_gpio.c | |
| parent | 8433dee02777e81144a520143fa937672a6936e0 (diff) | |
| download | focaccia-qemu-811595a2d4ab8c6354857a50ffd29fafce52a892.tar.gz focaccia-qemu-811595a2d4ab8c6354857a50ffd29fafce52a892.zip | |
target-arm: Fix reset and migration of TTBCR(S)
Commit 6459b94c26dd666badb3 broke reset and migration of the AArch32 TTBCR(S) register if the guest used non-LPAE page tables. This is because the AArch32 TTBCR register definition is marked as ARM_CP_ALIAS, meaning that the AArch64 variant has to handle migration and reset. Although AArch64 TCR_EL3 doesn't need to care about the mask and base_mask fields, AArch32 may do so, and so we must use the special TTBCR reset and raw write functions to ensure they are set correctly. This doesn't affect TCR_EL2, because the AArch32 equivalent of that is HTCR, which never uses the non-LPAE page table variant. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Pranith Kumar <bobby.prani+qemu@gmail.com> Reviewed-by: Sergey Fedorov <sergey.fedorov@linaro.org> Message-id: 1465488181-31977-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw/gpio/omap_gpio.c')
0 files changed, 0 insertions, 0 deletions