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authorAnthony Liguori <aliguori@us.ibm.com>2012-03-14 16:47:49 -0500
committerAnthony Liguori <aliguori@us.ibm.com>2012-03-14 16:47:49 -0500
commitaea6ff7fa07b046fb9f43d6262d6e34b77e8437e (patch)
treedd3043d1742273a95fa7fc5e99b8d5ffe0c710e5 /hw/highbank.c
parent9e4dd565b46749d5e6d5cf87bfd84f1917c68319 (diff)
parentdd83b06ae61cfa2dc4381ab49f365bd0995fc930 (diff)
downloadfocaccia-qemu-aea6ff7fa07b046fb9f43d6262d6e34b77e8437e.tar.gz
focaccia-qemu-aea6ff7fa07b046fb9f43d6262d6e34b77e8437e.zip
Merge remote-tracking branch 'afaerber/qom-cpu.v5' into staging
* afaerber/qom-cpu.v5: (43 commits)
  qom: Introduce CPU class
  Rename CPUState -> CPUArchState
  xtensa hw/: Don't use CPUState
  sparc hw/: Don't use CPUState
  sh4 hw/: Don't use CPUState
  s390x hw/: Don't use CPUState
  ppc hw/: Don't use CPUState
  mips hw/: Don't use CPUState
  microblaze hw/: Don't use CPUState
  m68k hw/: Don't use CPUState
  lm32 hw/: Don't use CPUState
  i386 hw/: Don't use CPUState
  cris hw/: Don't use CPUState
  arm hw/: Don't use CPUState
  alpha hw/: Don't use CPUState
  xtensa-semi: Don't use CPUState
  m68k-semi: Don't use CPUState
  arm-semi: Don't use CPUState
  target-xtensa: Don't overuse CPUState
  target-unicore32: Don't overuse CPUState
  ...
Diffstat (limited to 'hw/highbank.c')
-rw-r--r--hw/highbank.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/hw/highbank.c b/hw/highbank.c
index 489c00e5b9..906eed5a47 100644
--- a/hw/highbank.c
+++ b/hw/highbank.c
@@ -37,12 +37,12 @@
 /* Board init.  */
 static void highbank_cpu_reset(void *opaque)
 {
-    CPUState *env = opaque;
+    CPUARMState *env = opaque;
 
     env->cp15.c15_config_base_address = GIC_BASE_ADDR;
 }
 
-static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info)
+static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
 {
     int n;
     uint32_t smpboot[] = {
@@ -66,7 +66,7 @@ static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info)
     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
 }
 
-static void hb_reset_secondary(CPUState *env, const struct arm_boot_info *info)
+static void hb_reset_secondary(CPUARMState *env, const struct arm_boot_info *info)
 {
     switch (info->nb_cpus) {
     case 4:
@@ -196,7 +196,7 @@ static void highbank_init(ram_addr_t ram_size,
                      const char *kernel_filename, const char *kernel_cmdline,
                      const char *initrd_filename, const char *cpu_model)
 {
-    CPUState *env = NULL;
+    CPUARMState *env = NULL;
     DeviceState *dev;
     SysBusDevice *busdev;
     qemu_irq *irqp;