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authorPeter Maydell <peter.maydell@linaro.org>2017-06-02 11:51:48 +0100
committerPeter Maydell <peter.maydell@linaro.org>2017-06-02 11:51:48 +0100
commit790a11503cfb5e1dcd031ea2212bbebae4ca3cec (patch)
tree5f72294b16a958db8c428a243f74f4d809386554 /hw/i2c/imx_i2c.c
parent3a00d560bcfca7ad04327062c1986a016c104b1f (diff)
downloadfocaccia-qemu-790a11503cfb5e1dcd031ea2212bbebae4ca3cec.tar.gz
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arm: All M profile cores are PMSA
All M profile CPUs are PMSA, so set the feature bit.
(We haven't actually implemented the M profile MPU register
interface yet, but setting this feature bit gives us closer
to correct behaviour for the MPU-disabled case.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1493122030-32191-11-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw/i2c/imx_i2c.c')
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