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authorJim Shu <jim.shu@sifive.com>2024-11-20 23:39:33 +0800
committerAlistair Francis <alistair.francis@wdc.com>2024-12-20 11:22:47 +1000
commitb4132a9e62978e247bce66e70499c4e2cad8d870 (patch)
treea9efc023a17630dd15c0b9de7067cfc321c39597 /hw/i2c/omap_i2c.c
parentd2ed9fffba07a7ce87f33d5b9662e3e8eadb11d4 (diff)
downloadfocaccia-qemu-b4132a9e62978e247bce66e70499c4e2cad8d870.tar.gz
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hw/riscv: Support to load DTB after 3GB memory on 64-bit system.
Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
system doesn't have 32-bit addressable issue, we just load DTB to the end
of dram in 64-bit system.

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241120153935.24706-2-jim.shu@sifive.com>
[ Changes by AF
 -  Store fdt_load_addr_hi32 in the reset vector
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/i2c/omap_i2c.c')
0 files changed, 0 insertions, 0 deletions