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| author | Max Filippov <jcmvbkbc@gmail.com> | 2020-06-30 19:27:02 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2020-08-21 12:48:15 -0700 |
| commit | cfa9f0518144c0ea30f51fd2f203a09dd0a40cd9 (patch) | |
| tree | 4a29bea5fe5092cae79d9d90027a4d3fed6c05f9 /hw/i2c/omap_i2c.c | |
| parent | de6b55cbda2a26fb8889c8a8b44c139d7e106dce (diff) | |
| download | focaccia-qemu-cfa9f0518144c0ea30f51fd2f203a09dd0a40cd9.tar.gz focaccia-qemu-cfa9f0518144c0ea30f51fd2f203a09dd0a40cd9.zip | |
target/xtensa: add DFPU registers and opcodes
DFPU may be configured with 32-bit or with 64-bit registers. Xtensa ISA does not specify how single-precision values are stored in 64-bit registers. Existing implementations store them in the low half of the registers. Add value extraction and write back to single-precision opcodes. Add new double precision opcodes. Add 64-bit register file. Add 64-bit values dumping to the xtensa_cpu_dump_state. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'hw/i2c/omap_i2c.c')
0 files changed, 0 insertions, 0 deletions