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authorMax Filippov <jcmvbkbc@gmail.com>2020-06-30 14:52:25 -0700
committerMax Filippov <jcmvbkbc@gmail.com>2020-08-21 12:48:15 -0700
commite95ef43181b49a401d163729d0d96f304525dfe7 (patch)
tree17b1eec6333d72b90f255cc3f2ba9c4b86349421 /hw/i2c/omap_i2c.c
parent6ac269c33cd50679ed37b0bafcef0a95b76b1543 (diff)
downloadfocaccia-qemu-e95ef43181b49a401d163729d0d96f304525dfe7.tar.gz
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tests/tcg/xtensa: update test_fp0_arith for DFPU
DFPU arithmetic opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the arithmetic tests.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'hw/i2c/omap_i2c.c')
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