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| author | Gerd Hoffmann <kraxel@redhat.com> | 2020-06-19 11:19:00 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2020-06-24 17:18:28 -0400 |
| commit | 0575c2fd6ddeba1fbe6e4dca959917895aa8ee31 (patch) | |
| tree | 864eb612b7a630b9da5a0e3211f5f61dc33f408e /hw/i386/fw_cfg.c | |
| parent | df0f3d134a92cbbe07ccbfc017f39ed2dbcc6a3f (diff) | |
| download | focaccia-qemu-0575c2fd6ddeba1fbe6e4dca959917895aa8ee31.tar.gz focaccia-qemu-0575c2fd6ddeba1fbe6e4dca959917895aa8ee31.zip | |
acpi: factor out fw_cfg_add_acpi_dsdt()
Add helper function to add fw_cfg device, also move code to hw/i386/fw_cfg.c. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20200619091905.21676-8-kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/i386/fw_cfg.c')
| -rw-r--r-- | hw/i386/fw_cfg.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index da60ada594..c55abfb01a 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -15,6 +15,7 @@ #include "qemu/osdep.h" #include "sysemu/numa.h" #include "hw/acpi/acpi.h" +#include "hw/acpi/aml-build.h" #include "hw/firmware/smbios.h" #include "hw/i386/fw_cfg.h" #include "hw/timer/hpet.h" @@ -179,3 +180,30 @@ void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg) *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); } + +void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg) +{ + /* + * when using port i/o, the 8-bit data register *always* overlaps + * with half of the 16-bit control register. Hence, the total size + * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the + * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 + */ + Object *obj = OBJECT(fw_cfg); + uint8_t io_size = object_property_get_bool(obj, "dma_enabled", NULL) ? + ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : + FW_CFG_CTL_SIZE; + Aml *dev = aml_device("FWCF"); + Aml *crs = aml_resource_template(); + + aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); + + /* device present, functioning, decoding, not shown in UI */ + aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); + + aml_append(crs, + aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)); + + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(scope, dev); +} |