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| author | Zhenzhong Duan <zhenzhong.duan@intel.com> | 2024-12-12 16:37:55 +0800 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2025-01-15 13:06:35 -0500 |
| commit | aa68a9fbdb81c47c2a48a3199559df470c3d9eba (patch) | |
| tree | 0b8779b2b4a0086e331bcb820e93e5733a369957 /hw/i386/intel_iommu_internal.h | |
| parent | 81ab964f21620db32558277f220eb0d803c14109 (diff) | |
| download | focaccia-qemu-aa68a9fbdb81c47c2a48a3199559df470c3d9eba.tar.gz focaccia-qemu-aa68a9fbdb81c47c2a48a3199559df470c3d9eba.zip | |
intel_iommu: Introduce a property x-flts for stage-1 translation
Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities related to scalable mode translation, thus there are multiple combinations. This vIOMMU implementation wants to simplify it with a new property "x-flts". When turned on in scalable mode, stage-1 translation is supported. When turned on in legacy mode, throw out error. With stage-1 translation support exposed to user, also accurate the pasid entry check in vtd_pe_type_check(). Suggested-by: Jason Wang <jasowang@redhat.com> Signed-off-by: Yi Liu <yi.l.liu@intel.com> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Message-Id: <20241212083757.605022-19-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/i386/intel_iommu_internal.h')
| -rw-r--r-- | hw/i386/intel_iommu_internal.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 2c977aa7da..e8b211e8b0 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -195,6 +195,7 @@ #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_SMTS (1ULL << 43) #define VTD_ECAP_SLTS (1ULL << 46) +#define VTD_ECAP_FLTS (1ULL << 47) /* CAP_REG */ /* (offset >> 4) << 24 */ @@ -211,6 +212,7 @@ #define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35)) #define VTD_CAP_DRAIN_WRITE (1ULL << 54) #define VTD_CAP_DRAIN_READ (1ULL << 55) +#define VTD_CAP_FS1GP (1ULL << 56) #define VTD_CAP_DRAIN (VTD_CAP_DRAIN_READ | VTD_CAP_DRAIN_WRITE) #define VTD_CAP_CM (1ULL << 7) #define VTD_PASID_ID_SHIFT 20 |