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| author | Yi Liu <yi.l.liu@intel.com> | 2024-12-12 16:37:43 +0800 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2025-01-15 13:06:12 -0500 |
| commit | eb9da9d2632839c386ecbfc50f78032c9f3a75a4 (patch) | |
| tree | d5f71b173cfd85d8a1592b1c63f18dfe1f9d6dc2 /hw/i386/intel_iommu_internal.h | |
| parent | eda4c9b5b3c46f8d4d6a628cc7a588f187f30050 (diff) | |
| download | focaccia-qemu-eb9da9d2632839c386ecbfc50f78032c9f3a75a4.tar.gz focaccia-qemu-eb9da9d2632839c386ecbfc50f78032c9f3a75a4.zip | |
intel_iommu: Implement stage-1 translation
This adds stage-1 page table walking to support stage-1 only translation in scalable mode. Signed-off-by: Yi Liu <yi.l.liu@intel.com> Co-developed-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-7-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/i386/intel_iommu_internal.h')
| -rw-r--r-- | hw/i386/intel_iommu_internal.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e810b0071f..86d3354198 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -320,6 +320,15 @@ typedef enum VTDFaultReason { VTD_FR_PASID_ENTRY_P = 0x59, VTD_FR_PASID_TABLE_ENTRY_INV = 0x5b, /*Invalid PASID table entry */ + /* Fail to access a first-level paging entry (not FS_PML4E) */ + VTD_FR_FS_PAGING_ENTRY_INV = 0x70, + VTD_FR_FS_PAGING_ENTRY_P = 0x71, + /* Non-zero reserved field in present first-stage paging entry */ + VTD_FR_FS_PAGING_ENTRY_RSVD = 0x72, + VTD_FR_PASID_ENTRY_FSPTPTR_INV = 0x73, /* Invalid FSPTPTR in PASID entry */ + VTD_FR_FS_PAGING_ENTRY_US = 0x81, /* Privilege violation */ + VTD_FR_SM_WRITE = 0x85, /* No write permission */ + /* Output address in the interrupt address range for scalable mode */ VTD_FR_SM_INTERRUPT_ADDR = 0x87, VTD_FR_MAX, /* Guard */ @@ -438,6 +447,22 @@ typedef union VTDInvDesc VTDInvDesc; (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) +/* Rsvd field masks for fpte */ +#define VTD_FS_UPPER_IGNORED 0xfff0000000000000ULL +#define VTD_FPTE_PAGE_L1_RSVD_MASK(aw) \ + (~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED)) +#define VTD_FPTE_PAGE_L2_RSVD_MASK(aw) \ + (~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED)) +#define VTD_FPTE_PAGE_L3_RSVD_MASK(aw) \ + (~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED)) +#define VTD_FPTE_PAGE_L4_RSVD_MASK(aw) \ + (0x80ULL | ~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED)) + +#define VTD_FPTE_LPAGE_L2_RSVD_MASK(aw) \ + (0x1fe000ULL | ~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED)) +#define VTD_FPTE_LPAGE_L3_RSVD_MASK(aw) \ + (0x3fffe000ULL | ~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED)) + /* Masks for PIOTLB Invalidate Descriptor */ #define VTD_INV_DESC_PIOTLB_G (3ULL << 4) #define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4) @@ -530,6 +555,15 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_PASID_ENTRY_AW 7ULL /* Adjusted guest-address-width */ #define VTD_SM_PASID_ENTRY_DID(val) ((val) & VTD_DOMAIN_ID_MASK) +#define VTD_SM_PASID_ENTRY_FLPM 3ULL +#define VTD_SM_PASID_ENTRY_FLPTPTR (~0xfffULL) + +/* First Level Paging Structure */ +/* Masks for First Level Paging Entry */ +#define VTD_FL_P 1ULL +#define VTD_FL_RW (1ULL << 1) +#define VTD_FL_US (1ULL << 2) + /* Second Level Page Translation Pointer*/ #define VTD_SM_PASID_ENTRY_SLPTPTR (~0xfffULL) |