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| author | Fabian Aggeler <aggelerf@ethz.ch> | 2015-05-12 11:57:17 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-05-12 11:57:17 +0100 |
| commit | 8150847061f8d2606101bfff77cc6ec86b081ab0 (patch) | |
| tree | 8447b726a34d0a104d2282145e3eb3f004f6b3d2 /hw/intc/arm_gic_kvm.c | |
| parent | 08efa9f2d1bb27d64fbedcc2879ca45ae6832c20 (diff) | |
| download | focaccia-qemu-8150847061f8d2606101bfff77cc6ec86b081ab0.tar.gz focaccia-qemu-8150847061f8d2606101bfff77cc6ec86b081ab0.zip | |
hw/intc/arm_gic: Restrict priority view
GICs with Security Extensions restrict the non-secure view of the interrupt priority and priority mask registers. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-11-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-15-git-send-email-greg.bellows@linaro.org [PMM: minor code tweaks; fixed missing masking in gic_set_priority_mask and gic_set_priority] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/arm_gic_kvm.c')
| -rw-r--r-- | hw/intc/arm_gic_kvm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 33e6a87b3c..2cb7d255d2 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -251,7 +251,7 @@ static void translate_priority(GICState *s, int irq, int cpu, if (to_kernel) { *field = GIC_GET_PRIORITY(irq, cpu) & 0xff; } else { - gic_set_priority(s, cpu, irq, *field & 0xff); + gic_set_priority(s, cpu, irq, *field & 0xff, MEMTXATTRS_UNSPECIFIED); } } |