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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-05-24 13:42:48 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-06-17 15:13:19 +0100 |
| commit | 0edfcc9ec06fbbcc154cce64748752a5c565a32c (patch) | |
| tree | cbf0438772a74fde51ae90459fdcfbd5416c3ff5 /hw/intc/arm_gicv3_dist.c | |
| parent | e40f60730a208338057d51bfc6c98f89af8eab2d (diff) | |
| download | focaccia-qemu-0edfcc9ec06fbbcc154cce64748752a5c565a32c.tar.gz focaccia-qemu-0edfcc9ec06fbbcc154cce64748752a5c565a32c.zip | |
hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1
The GICv3 specification says that the GICD_TYPER.SecurityExtn bit is RAZ if GICD_CTLR.DS is 1. We were incorrectly making it RAZ if the security extension is unsupported. "Security extension unsupported" always implies GICD_CTLR.DS == 1, but the guest can also set DS on a GIC which does support the security extension. Fix the condition to correctly check the GICD_CTLR.DS bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190524124248.28394-3-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/arm_gicv3_dist.c')
| -rw-r--r-- | hw/intc/arm_gicv3_dist.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index e6fe4905fd..b65f56f903 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -378,8 +378,14 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset, * ITLinesNumber == (num external irqs / 32) - 1 */ int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1; + /* + * SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and + * "security extensions not supported" always implies DS == 1, + * so we only need to check the DS bit. + */ + bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS); - *data = (1 << 25) | (1 << 24) | (s->security_extn << 10) | + *data = (1 << 25) | (1 << 24) | (sec_extn << 10) | (0xf << 19) | itlinesnumber; return MEMTX_OK; } |