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authorPeter Maydell <peter.maydell@linaro.org>2022-04-08 15:15:13 +0100
committerPeter Maydell <peter.maydell@linaro.org>2022-04-22 09:19:24 +0100
commit50a3a309e12789e28a3c4e260348ed7305c28b99 (patch)
tree4e16a119a46832bbbdd24f44225a74f4b1255b25 /hw/intc/arm_gicv3_redist.c
parent671927a1165fa1a1dc6ebb413f58615f62105d6d (diff)
downloadfocaccia-qemu-50a3a309e12789e28a3c4e260348ed7305c28b99.tar.gz
focaccia-qemu-50a3a309e12789e28a3c4e260348ed7305c28b99.zip
hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers
We use the common function gicv3_idreg() to supply the CoreSight ID
register values for the GICv3 for the copies of these ID registers in
the distributor, redistributor and ITS register frames.  This isn't
quite correct, because while most of the register values are the
same, the PIDR0 value should vary to indicate which of these three
frames it is.  (You can see this and also the correct values of these
PIDR0 registers by looking at the GIC-600 or GIC-700 TRMs, for
example.)

Make gicv3_idreg() take an extra argument for the PIDR0 value.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-5-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/arm_gicv3_redist.c')
-rw-r--r--hw/intc/arm_gicv3_redist.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 412a04f59c..dc9729e839 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -234,7 +234,7 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset,
         *data = cs->gicr_nsacr;
         return MEMTX_OK;
     case GICR_IDREGS ... GICR_IDREGS + 0x2f:
-        *data = gicv3_idreg(offset - GICR_IDREGS);
+        *data = gicv3_idreg(offset - GICR_IDREGS, GICV3_PIDR0_REDIST);
         return MEMTX_OK;
     default:
         return MEMTX_ERROR;