diff options
| author | Shashi Mallela <shashi.mallela@linaro.org> | 2021-09-13 16:07:23 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-09-13 16:07:54 +0100 |
| commit | 1b08e436d0deaece35f7fa21aba6e6afe26cb3ac (patch) | |
| tree | fd8926359e2e7f8da092e23f063d72919b03b9a8 /hw/intc/gicv3_internal.h | |
| parent | 18f6290a6a95b2b16ab061bfd92274f6ba2a821b (diff) | |
| download | focaccia-qemu-1b08e436d0deaece35f7fa21aba6e6afe26cb3ac.tar.gz focaccia-qemu-1b08e436d0deaece35f7fa21aba6e6afe26cb3ac.zip | |
hw/intc: GICv3 ITS register definitions added
Defined descriptors for ITS device table,collection table and ITS command queue entities.Implemented register read/write functions, extract ITS table parameters and command queue parameters,extended gicv3 common to capture qemu address space(which host the ITS table platform memories required for subsequent ITS processing) and initialize the same in ITS device. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Message-id: 20210910143951.92242-3-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/gicv3_internal.h')
| -rw-r--r-- | hw/intc/gicv3_internal.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index b99bf9db46..92e0a4fa68 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -258,6 +258,20 @@ FIELD(GITS_BASER, INNERCACHE, 59, 3) FIELD(GITS_BASER, INDIRECT, 62, 1) FIELD(GITS_BASER, VALID, 63, 1) +FIELD(GITS_CBASER, SIZE, 0, 8) +FIELD(GITS_CBASER, SHAREABILITY, 10, 2) +FIELD(GITS_CBASER, PHYADDR, 12, 40) +FIELD(GITS_CBASER, OUTERCACHE, 53, 3) +FIELD(GITS_CBASER, INNERCACHE, 59, 3) +FIELD(GITS_CBASER, VALID, 63, 1) + +FIELD(GITS_CREADR, STALLED, 0, 1) +FIELD(GITS_CREADR, OFFSET, 5, 15) + +FIELD(GITS_CWRITER, RETRY, 0, 1) +FIELD(GITS_CWRITER, OFFSET, 5, 15) + +FIELD(GITS_CTLR, ENABLED, 0, 1) FIELD(GITS_CTLR, QUIESCENT, 31, 1) FIELD(GITS_TYPER, PHYSICAL, 0, 1) @@ -269,6 +283,13 @@ FIELD(GITS_TYPER, PTA, 19, 1) FIELD(GITS_TYPER, CIDBITS, 32, 4) FIELD(GITS_TYPER, CIL, 36, 1) +#define GITS_IDREGS 0xFFD0 + +#define ITS_CTLR_ENABLED (1U) /* ITS Enabled */ + +#define GITS_BASER_RO_MASK (R_GITS_BASER_ENTRYSIZE_MASK | \ + R_GITS_BASER_TYPE_MASK) + #define GITS_BASER_PAGESIZE_4K 0 #define GITS_BASER_PAGESIZE_16K 1 #define GITS_BASER_PAGESIZE_64K 2 @@ -276,6 +297,14 @@ FIELD(GITS_TYPER, CIL, 36, 1) #define GITS_BASER_TYPE_DEVICE 1ULL #define GITS_BASER_TYPE_COLLECTION 4ULL +#define GITS_PAGE_SIZE_4K 0x1000 +#define GITS_PAGE_SIZE_16K 0x4000 +#define GITS_PAGE_SIZE_64K 0x10000 + +#define L1TABLE_ENTRY_SIZE 8 + +#define GITS_CMDQ_ENTRY_SIZE 32 + /** * Default features advertised by this version of ITS */ |