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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-06-17 15:23:47 +0100 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-06-17 15:23:51 +0100 |
| commit | 359fbe65e01e13f582d3b9103e7c3ec5ac367a18 (patch) | |
| tree | 5dc875f829bcdb3e3aab7480542a0ebe9e41b98b /hw/intc/gicv3_internal.h | |
| parent | c84428b33fc2d88f17c3f599a9e5d17ae23422c1 (diff) | |
| download | focaccia-qemu-359fbe65e01e13f582d3b9103e7c3ec5ac367a18.tar.gz focaccia-qemu-359fbe65e01e13f582d3b9103e7c3ec5ac367a18.zip | |
hw/intc/arm_gicv3: Implement GICv3 CPU interface registers
Implement the CPU interface registers for the GICv3; these are CPU system registers, not MMIO registers. This commit implements all the registers which are simple accessors for GIC state, but not those which act as interfaces for acknowledging, dismissing or generating interrupts. (Those will be added in a later commit.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-16-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/gicv3_internal.h')
| -rw-r--r-- | hw/intc/gicv3_internal.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index a6f443cef6..13f951c81f 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -211,6 +211,7 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, unsigned size, MemTxAttrs attrs); void gicv3_dist_set_irq(GICv3State *s, int irq, int level); void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level); +void gicv3_init_cpuif(GICv3State *s); /** * gicv3_cpuif_update: |