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| author | Jinjie Ruan <ruanjinjie@huawei.com> | 2024-04-19 14:32:59 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-04-25 10:21:05 +0100 |
| commit | 2e0be5f6b122e3dca53b926514287ffcead2689c (patch) | |
| tree | 14ec2a9a8f167556eaec5b5eff5f0a86405c8636 /hw/intc/m68k_irqc.c | |
| parent | 963e4e3648e0601a8f0b288edaf524b3c98fffbd (diff) | |
| download | focaccia-qemu-2e0be5f6b122e3dca53b926514287ffcead2689c.tar.gz focaccia-qemu-2e0be5f6b122e3dca53b926514287ffcead2689c.zip | |
target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI
Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-9-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/m68k_irqc.c')
0 files changed, 0 insertions, 0 deletions