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| author | Jinjie Ruan <ruanjinjie@huawei.com> | 2024-04-19 14:32:57 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-04-25 10:21:04 +0100 |
| commit | cbf817a2ff7dc12b62e0bccc15ae93369ea5829e (patch) | |
| tree | e38ab2c44c32c3d997c98e66d606956a26229c65 /hw/intc/m68k_irqc.c | |
| parent | 4833c75611e334164b970c79be95f239ce676ab1 (diff) | |
| download | focaccia-qemu-cbf817a2ff7dc12b62e0bccc15ae93369ea5829e.tar.gz focaccia-qemu-cbf817a2ff7dc12b62e0bccc15ae93369ea5829e.zip | |
target/arm: Implement ALLINT MSR (immediate)
Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The EL0 check is necessary to ALLINT, and the EL1 check is necessary when imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the unconditional write to pc and use raise_exception_ra to unwind. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-5-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/m68k_irqc.c')
0 files changed, 0 insertions, 0 deletions