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| author | Jim Shu <jim.shu@sifive.com> | 2025-09-24 15:48:18 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-10-03 13:15:14 +1000 |
| commit | 0b16c7b6a854d461cdfd418769b51d58e43dd92a (patch) | |
| tree | 600387b41fefc65e44ebcb45b06dc9e3a94fe755 /hw/intc/riscv_aplic.c | |
| parent | 84c1605b7606d810ded4c1c3a2717f158dc89e3f (diff) | |
| download | focaccia-qemu-0b16c7b6a854d461cdfd418769b51d58e43dd92a.tar.gz focaccia-qemu-0b16c7b6a854d461cdfd418769b51d58e43dd92a.zip | |
target/riscv: Fix ssamoswap error handling
Follow the RISC-V CFI v1.0 spec [1] to fix the exception type when ssamoswap is disabled by xSSE. [1] RISC-V CFI spec v1.0, ch2.7 Atomic Swap from a Shadow Stack Location Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250924074818.230010-4-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc/riscv_aplic.c')
0 files changed, 0 insertions, 0 deletions