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| author | Max Chou <max.chou@sifive.com> | 2025-06-27 21:30:13 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-07-04 21:09:49 +1000 |
| commit | b5092b3db23391d6ee770123715b76b85169d977 (patch) | |
| tree | d62bcdbfa53e334b9804ad19387bb7b1a6409708 /hw/intc/riscv_aplic.c | |
| parent | 29abd3d112c380b8019a77ebad65f61addfb812d (diff) | |
| download | focaccia-qemu-b5092b3db23391d6ee770123715b76b85169d977.tar.gz focaccia-qemu-b5092b3db23391d6ee770123715b76b85169d977.zip | |
target/riscv: rvv: Fix missing exit TB flow for ldff_trans
According to the V spec, the vector fault-only-first load instructions may change the VL CSR. So the ldff_trans TCG translation function should generate the lookup_and_goto_ptr flow as the vsetvl/vsetvli translation function to make sure the vl_eq_vlmax TB flag is correct. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250627133013.443997-1-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc/riscv_aplic.c')
0 files changed, 0 insertions, 0 deletions