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| author | Jim Shu <jim.shu@sifive.com> | 2025-09-24 15:48:16 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-10-03 13:15:14 +1000 |
| commit | c851052a77fd79300708df2070297b5428b4be8d (patch) | |
| tree | cbd7db1f51c0d56b28f2fe3be17c222ba8479ed2 /hw/intc/riscv_aplic.c | |
| parent | a86d3352ab70f33f5feabbf9bad9450d3c19d0bf (diff) | |
| download | focaccia-qemu-c851052a77fd79300708df2070297b5428b4be8d.tar.gz focaccia-qemu-c851052a77fd79300708df2070297b5428b4be8d.zip | |
target/riscv: Fix the mepc when sspopchk triggers the exception
When sspopchk is in the middle of TB and triggers the SW check exception, it should update PC from gen_update_pc(). If not, RISC-V mepc CSR will get wrong PC address which is still at the start of TB. Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250924074818.230010-2-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc/riscv_aplic.c')
0 files changed, 0 insertions, 0 deletions