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| author | Anup Patel <apatel@ventanamicro.com> | 2022-08-20 09:59:58 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-09-07 09:18:33 +0200 |
| commit | dc9acc9ce4add37bc5b4437ae9117c318b4f09d4 (patch) | |
| tree | d48382a6a930a95a0a1e8860059614eb7828d673 /hw/intc/riscv_imsic.c | |
| parent | e0dea2f55f678a1aa1dab3a25c13f52d68b4ec2b (diff) | |
| download | focaccia-qemu-dc9acc9ce4add37bc5b4437ae9117c318b4f09d4.tar.gz focaccia-qemu-dc9acc9ce4add37bc5b4437ae9117c318b4f09d4.zip | |
target/riscv: Use official extension names for AIA CSRs
The arch review of AIA spec is completed and we now have official extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode AIA CSRs). Refer, section 1.6 of the latest AIA v0.3.1 stable specification at https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32/riscv-interrupts-032.pdf) Based on above, we update QEMU RISC-V to: 1) Have separate config options for Smaia and Ssaia extensions which replace RISCV_FEATURE_AIA in CPU features 2) Not generate AIA INTC compatible string in virt machine Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220820042958.377018-1-apatel@ventanamicro.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc/riscv_imsic.c')
| -rw-r--r-- | hw/intc/riscv_imsic.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 8615e4cc1d..4d4d5b50ca 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -344,9 +344,11 @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp) /* Force select AIA feature and setup CSR read-modify-write callback */ if (env) { - riscv_set_feature(env, RISCV_FEATURE_AIA); if (!imsic->mmode) { + rcpu->cfg.ext_ssaia = true; riscv_cpu_set_geilen(env, imsic->num_pages - 1); + } else { + rcpu->cfg.ext_smaia = true; } riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S, riscv_imsic_rmw, imsic); |