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| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2013-06-11 10:58:25 +1000 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2013-06-18 09:44:59 +0200 |
| commit | 6327c221fff955ee979559ec85c148963e06d78f (patch) | |
| tree | 87ce0cab3518107edc7d831ad0eec767bc50bd1c /hw/intc/xilinx_intc.c | |
| parent | 37a011e9bade7bcbdd41addffc7c94cbf628404c (diff) | |
| download | focaccia-qemu-6327c221fff955ee979559ec85c148963e06d78f.tar.gz focaccia-qemu-6327c221fff955ee979559ec85c148963e06d78f.zip | |
intc/xilinx_intc: Don't clear level sens. IRQs without ACK
For level sensitive interrupts, ISR bits are cleared when the input pin is lowered. This is incorrect. Only software can clear ISR bits (via IAR or direct write to ISR with !MER(2)). Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'hw/intc/xilinx_intc.c')
| -rw-r--r-- | hw/intc/xilinx_intc.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 5df7008e2f..d243a0015f 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -135,13 +135,7 @@ static void irq_handler(void *opaque, int irq, int level) return; } - /* Update source flops. Don't clear unless level triggered. - Edge triggered interrupts only go away when explicitely acked to - the interrupt controller. */ - if (!(p->c_kind_of_intr & (1 << irq)) || level) { - p->regs[R_ISR] &= ~(1 << irq); - p->regs[R_ISR] |= (level << irq); - } + p->regs[R_ISR] |= (level << irq); update_irq(p); } |