Merge tag 'pull-target-arm-20230113' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 hw/arm/stm32f405: correctly describe the memory layout
 hw/arm: Add Olimex H405 board
 cubieboard: Support booting from an SD card image with u-boot on it
 target/arm: Fix sve_probe_page
 target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled
 various code cleanups

# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmPBZmYZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3rDdD/9GlrH14yP/2WQZJVJxzXkf
# ltO1pvX/AfeNPGy3F8T+kncKspIUeJ8BQNrZKYPWkH1WgAAT3lVH/cUbAlr8UD6W
# p2t64ZdQAURuEw3kqtyUVOUeIxzg29cEQyW/9uchA3QPb9xDtiq6KLpAzifDzo6o
# 2JE4/NytUJSKxFr5hnyxRTtOYPEMLShBSPvPzU0/BPq7VPyPhT4rqojhpx9uZpVc
# h4mfVm9cpF0y3ThBR37M0nhEGJywB/6zOsZ49bm06MFFTwasZ4P0w0fcKhbvrFvX
# PHVlNOvyT1oxch5ErN+KULZLByiWy0/Nw85V8P9R+1hU6nncQPM5paB6Y5HUCTKv
# wa9gp38V8323fsHg2EEV/PYRdcmRWSBHOq9HPDjIIJlG9nvfXn9O69kDlhnst44b
# Fz27XiGJOKY+f20l0J0KzaOnnjw54aeo5tc5WUDbBiZ/btsAHBGQAg7JghmoLkhb
# rlvJFgGdG99IuBqJH69dJQ8n/R9bGDRu6X0i1ir3d3C2nY9HYaWUZMyyxOw9dV43
# igQHupOzyYbSyy9+40xz611P0h2k2d90P61Vi41D9ig4Du+I4Vftjqj9mi/Z829k
# W1JE5wpKWcDeIXFYLWCZuiOyTCCFBWiWgDJz/zQf7AYma0AWA9gpKrTh2+3EFfqy
# VsvMR2T6kmS3FId50bW5OQ==
# =D+ib
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 13 Jan 2023 14:10:46 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20230113' of https://git.linaro.org/people/pmaydell/qemu-arm: (38 commits)
  target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled
  hw/timer/xilinx_timer: Use XpsTimerState instead of 'struct timerblock'
  hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic'
  hw/misc/sbsa_ec: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
  hw/misc/sbsa_ec: Rename TYPE_SBSA_EC -> TYPE_SBSA_SECURE_EC
  hw/arm/npcm7xx: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
  hw/arm/bcm2836: Remove definitions generated by OBJECT_DECLARE_TYPE()
  hw/arm/stellaris: Use CamelCase for STELLARIS_ADC type name
  hw/arm/stellaris: Drop useless casts from void * to pointer
  hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type name
  hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP2_GPIO type name
  hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP1_GPIO type name
  hw/arm/omap: Drop useless casts from void * to pointer
  hw/gpio/omap_gpio: Add local variable to avoid embedded cast
  hw/arm/pxa: Avoid forward-declaring PXA2xxI2CState
  hw/arm: Remove unreachable code calling pflash_cfi01_register()
  hw/arm/vexpress: Remove dead code in vexpress_common_init()
  hw/arm/z2: Use the IEC binary prefix definitions
  hw/arm/omap_sx1: Use the IEC binary prefix definitions
  hw/arm/omap_sx1: Remove unused 'total_ram' definitions
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

1 files changed, 13 insertions, 15 deletions

diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index 4c4397b3d2..6e5012e66e 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -42,10 +42,10 @@
 #define R_MAX       8
 
 #define TYPE_XILINX_INTC "xlnx.xps-intc"
-DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC,
-                         TYPE_XILINX_INTC)
+typedef struct XpsIntc XpsIntc;
+DECLARE_INSTANCE_CHECKER(XpsIntc, XILINX_INTC, TYPE_XILINX_INTC)
 
-struct xlx_pic
+struct XpsIntc
 {
     SysBusDevice parent_obj;
 
@@ -62,7 +62,7 @@ struct xlx_pic
     uint32_t irq_pin_state;
 };
 
-static void update_irq(struct xlx_pic *p)
+static void update_irq(XpsIntc *p)
 {
     uint32_t i;
 
@@ -87,10 +87,9 @@ static void update_irq(struct xlx_pic *p)
     qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]);
 }
 
-static uint64_t
-pic_read(void *opaque, hwaddr addr, unsigned int size)
+static uint64_t pic_read(void *opaque, hwaddr addr, unsigned int size)
 {
-    struct xlx_pic *p = opaque;
+    XpsIntc *p = opaque;
     uint32_t r = 0;
 
     addr >>= 2;
@@ -106,11 +105,10 @@ pic_read(void *opaque, hwaddr addr, unsigned int size)
     return r;
 }
 
-static void
-pic_write(void *opaque, hwaddr addr,
-          uint64_t val64, unsigned int size)
+static void pic_write(void *opaque, hwaddr addr,
+                      uint64_t val64, unsigned int size)
 {
-    struct xlx_pic *p = opaque;
+    XpsIntc *p = opaque;
     uint32_t value = val64;
 
     addr >>= 2;
@@ -154,7 +152,7 @@ static const MemoryRegionOps pic_ops = {
 
 static void irq_handler(void *opaque, int irq, int level)
 {
-    struct xlx_pic *p = opaque;
+    XpsIntc *p = opaque;
 
     /* edge triggered interrupt */
     if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) {
@@ -168,7 +166,7 @@ static void irq_handler(void *opaque, int irq, int level)
 
 static void xilinx_intc_init(Object *obj)
 {
-    struct xlx_pic *p = XILINX_INTC(obj);
+    XpsIntc *p = XILINX_INTC(obj);
 
     qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq);
@@ -179,7 +177,7 @@ static void xilinx_intc_init(Object *obj)
 }
 
 static Property xilinx_intc_properties[] = {
-    DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0),
+    DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -193,7 +191,7 @@ static void xilinx_intc_class_init(ObjectClass *klass, void *data)
 static const TypeInfo xilinx_intc_info = {
     .name          = TYPE_XILINX_INTC,
     .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(struct xlx_pic),
+    .instance_size = sizeof(XpsIntc),
     .instance_init = xilinx_intc_init,
     .class_init    = xilinx_intc_class_init,
 };