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authorPeter Crosthwaite <peter.crosthwaite@xilinx.com>2013-06-11 10:59:55 +1000
committerEdgar E. Iglesias <edgar.iglesias@gmail.com>2013-06-18 09:45:00 +0200
commitfa96d6142f7f1947717c7c45c4d3141e5ab55167 (patch)
tree8593a42aeae04b8a9290aebbfd14eef16f76954d /hw/intc/xilinx_intc.c
parent45fdd3bf5a00466cb0f762c638291a5446773dc9 (diff)
downloadfocaccia-qemu-fa96d6142f7f1947717c7c45c4d3141e5ab55167.tar.gz
focaccia-qemu-fa96d6142f7f1947717c7c45c4d3141e5ab55167.zip
intc/xilinx_intc: Inhibit write to ISR when HIE
When the Hardware Interrupt Enable (HIE) bit is set, software cannot
change ISR. Add write guard accordingly.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'hw/intc/xilinx_intc.c')
-rw-r--r--hw/intc/xilinx_intc.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index 09b445320b..ddedfa3796 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -116,6 +116,11 @@ pic_write(void *opaque, hwaddr addr,
         case R_CIE:
             p->regs[R_IER] &= ~value; /* Atomic clear ie.  */
             break;
+        case R_ISR:
+            if ((p->regs[R_MER] & 2)) {
+                break;
+            }
+            /* fallthrough */
         default:
             if (addr < ARRAY_SIZE(p->regs))
                 p->regs[addr] = value;