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| author | Nicholas Piggin <npiggin@gmail.com> | 2025-05-12 13:10:23 +1000 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-07-21 08:03:52 +0200 |
| commit | 9d466ab9b6f27a5d5b7a0ec5a7ad6f60e82fafda (patch) | |
| tree | a783d1950e227e5baafb35addba56fe1681651cb /hw/intc/xive.c | |
| parent | 14bcc5239f4d4780ec52881779161c62c46e7243 (diff) | |
| download | focaccia-qemu-9d466ab9b6f27a5d5b7a0ec5a7ad6f60e82fafda.tar.gz focaccia-qemu-9d466ab9b6f27a5d5b7a0ec5a7ad6f60e82fafda.zip | |
ppc/xive: Explicitly zero NSR after accepting
Have xive_tctx_accept clear NSR in one shot rather than masking out bits as they are tested, which makes it clear it's reset to 0, and does not have a partial NSR value in the register. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-15-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'hw/intc/xive.c')
| -rw-r--r-- | hw/intc/xive.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/hw/intc/xive.c b/hw/intc/xive.c index a0a60a24f5..b35d2ec179 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -68,13 +68,11 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) * If the interrupt was for a specific VP, reset the pending * buffer bit, otherwise clear the logical server indicator */ - if (regs[TM_NSR] & TM_NSR_GRP_LVL) { - regs[TM_NSR] &= ~TM_NSR_GRP_LVL; - } else { + if (!(regs[TM_NSR] & TM_NSR_GRP_LVL)) { alt_regs[TM_IPB] &= ~xive_priority_to_ipb(cppr); } - /* Drop the exception bit and any group/crowd */ + /* Clear the exception from NSR */ regs[TM_NSR] = 0; trace_xive_tctx_accept(tctx->cs->cpu_index, alt_ring, |