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| author | Glenn Miles <milesg@linux.ibm.com> | 2025-09-25 15:17:45 -0500 |
|---|---|---|
| committer | Harsh Prateek Bora <harshpb@linux.ibm.com> | 2025-09-28 23:39:19 +0530 |
| commit | 7197f6f7baf29fd76486920e5603e43b25880d3b (patch) | |
| tree | 8ce6959e404173f82af22121f1cbe6b1e8b67a83 /hw/intc/xive2.c | |
| parent | f7ec91c23906ca364650e95f2a28e0ef6c411386 (diff) | |
| download | focaccia-qemu-7197f6f7baf29fd76486920e5603e43b25880d3b.tar.gz focaccia-qemu-7197f6f7baf29fd76486920e5603e43b25880d3b.zip | |
hw/ppc: Support for an IBM PPE42 CPU decrementer
The IBM PPE42 processors support a 32-bit decrementer that can raise an external interrupt when DEC[0] transitions from a 0 to a -1 (a non-negative value to a negative value). It also continues decrementing even after this condition is met. The BookE timer is slightly different in that it raises an interrupt when the DEC value reaches 0 and stops decrementing at that point. Support a PPE42 version of the BookE timer by adding a new PPC_TIMER_PPE flag that has the timer code look for the transition from a non-negative value to a negative value and allows the value to continue decrementing. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925201758.652077-8-milesg@linux.ibm.com Message-ID: <20250925201758.652077-8-milesg@linux.ibm.com>
Diffstat (limited to 'hw/intc/xive2.c')
0 files changed, 0 insertions, 0 deletions