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| author | Doug Brown <doug@schmorgal.com> | 2024-09-13 15:31:47 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-09-13 15:31:47 +0100 |
| commit | 2215e297b9af4a42fefd1c014f7a3048995cea97 (patch) | |
| tree | 7093becb93c2d169e37ee0c7f51dcb92eeb349f6 /hw/intc | |
| parent | 676624d757abe0adcfa648ed3d4d44697997382f (diff) | |
| download | focaccia-qemu-2215e297b9af4a42fefd1c014f7a3048995cea97.tar.gz focaccia-qemu-2215e297b9af4a42fefd1c014f7a3048995cea97.zip | |
hw/net/can/xlnx-versal-canfd: Fix interrupt level
The interrupt level should be 0 or 1. The existing code was using the interrupt flags to determine the level. In the only machine currently supported (xlnx-versal-virt), the GICv3 was masking off all bits except bit 0 when applying it, resulting in the IRQ never being delivered. Signed-off-by: Doug Brown <doug@schmorgal.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Message-id: 20240827034927.66659-2-doug@schmorgal.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc')
0 files changed, 0 insertions, 0 deletions