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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2023-06-01 14:13:28 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2023-06-10 10:19:24 -0300 |
| commit | 32af01f83a763ccbba39c1cbc424e1b724d233df (patch) | |
| tree | 417c109b72f0b91495f4c8dfcec2b1935f02e542 /hw/intc | |
| parent | cce84fc9193e2566b4f7f9de5a13e7ed360d44d9 (diff) | |
| download | focaccia-qemu-32af01f83a763ccbba39c1cbc424e1b724d233df.tar.gz focaccia-qemu-32af01f83a763ccbba39c1cbc424e1b724d233df.zip | |
pnv/xive2: Add definition for the ESB cache configuration register
Add basic read/write support for the ESB cache configuration register
on P10. We don't model the ESB cache in qemu so reading/writing the
register won't do anything, but it avoids logging a guest error when
skiboot configures it:
qemu-system-ppc64 -machine powernv10 ... -d guest_errors
...
XIVE[0] - VC: invalid read @240
XIVE[0] - VC: invalid write @240
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230601121331.487207-3-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/pnv_xive2.c | 7 | ||||
| -rw-r--r-- | hw/intc/pnv_xive2_regs.h | 4 |
2 files changed, 11 insertions, 0 deletions
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 889e409929..a75ff270ac 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -955,6 +955,10 @@ static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset, val = xive->vc_regs[reg]; break; + case VC_ESBC_CFG: + val = xive->vc_regs[reg]; + break; + /* * EAS cache updates (not modeled) */ @@ -1046,6 +1050,9 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset, /* ESB update */ break; + case VC_ESBC_CFG: + break; + /* * EAS cache updates (not modeled) */ diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h index 8f1e0a1fde..7165dc8704 100644 --- a/hw/intc/pnv_xive2_regs.h +++ b/hw/intc/pnv_xive2_regs.h @@ -232,6 +232,10 @@ #define VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32, 35) #define VC_ESBC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63) /* 28-bit */ +/* ESBC configuration */ +#define X_VC_ESBC_CFG 0x148 +#define VC_ESBC_CFG 0x240 + /* EASC flush control register */ #define X_VC_EASC_FLUSH_CTRL 0x160 #define VC_EASC_FLUSH_CTRL 0x300 |