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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-03-18 13:24:41 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-03-18 13:24:41 +0000 |
| commit | a09863610aefe17390612b7d78d3fba20e43b53e (patch) | |
| tree | dcf39f4859c516dc5447ad3d0f1dc8f72af03ae3 /hw/intc | |
| parent | 1d60bb4b14601e38ed17384277aa4c30c57925d3 (diff) | |
| parent | 79d54c9eac04c554e3c081589542f801ace71797 (diff) | |
| download | focaccia-qemu-a09863610aefe17390612b7d78d3fba20e43b53e.tar.gz focaccia-qemu-a09863610aefe17390612b7d78d3fba20e43b53e.zip | |
Merge tag 'pull-target-arm-20220318' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Fix sve2 ldnt1 and stnt1 * Fix pauth_check_trap vs SEL2 * Fix handling of LPAE block descriptors * hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size * hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init() * nsis installer: List emulators in alphabetical order * nsis installer: Suppress "ANSI targets are deprecated" warning * nsis installer: Fix mouse-over descriptions for emulators * hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset * Improve M-profile vector table access logging * Xilinx ZynqMP: model CRF and APU control * Fix compile issues on modern Solaris # gpg: Signature made Fri 18 Mar 2022 13:18:20 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20220318' of https://git.linaro.org/people/pmaydell/qemu-arm: (21 commits) util/osdep: Remove some early cruft hw/i386/acpi-build: Avoid 'sun' identifier util/osdep: Avoid madvise proto on modern Solaris hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control hw/misc: Add a model of the Xilinx ZynqMP APU Control hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF hw/misc: Add a model of the Xilinx ZynqMP CRF target/arm: Make rvbar settable after realize hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area target/arm: Log fault address for M-profile faults target/arm: Log M-profile vector table accesses hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG nsis installer: Fix mouse-over descriptions for emulators nsis installer: Suppress "ANSI targets are deprecated" warning nsis installer: List emulators in alphabetical order hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init() hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size target/arm: Fix handling of LPAE block descriptors target/arm: Fix pauth_check_trap vs SEL2 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/Kconfig | 2 | ||||
| -rw-r--r-- | hw/intc/meson.build | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index ec8d4cec29..a7cf301eab 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -25,7 +25,7 @@ config APIC select MSI_NONBROKEN select I8259 -config ARM_GIC_TCG +config ARM_GICV3_TCG bool default y depends on ARM_GIC && TCG diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 81ccdb0d78..d6d012fb26 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -6,7 +6,7 @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files( 'arm_gicv3_common.c', 'arm_gicv3_its_common.c', )) -softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files( +softmmu_ss.add(when: 'CONFIG_ARM_GICV3_TCG', if_true: files( 'arm_gicv3.c', 'arm_gicv3_dist.c', 'arm_gicv3_its.c', @@ -28,7 +28,7 @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c')) specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) -specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c')) +specific_ss.add(when: 'CONFIG_ARM_GICV3_TCG', if_true: files('arm_gicv3_cpuif.c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) |