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| author | Sergey Makarov <s.makarov@syntacore.com> | 2024-09-18 17:02:29 +0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-30 11:22:08 +1000 |
| commit | a84be2baa9eca8bc500f866ad943b8f63dc99adf (patch) | |
| tree | e6a973eab31b9f8099e0d6b7f890c524e5cc8e44 /hw/intc | |
| parent | 41fc1f02947dd7a33b2c1d0e8474744b12f2514e (diff) | |
| download | focaccia-qemu-a84be2baa9eca8bc500f866ad943b8f63dc99adf.tar.gz focaccia-qemu-a84be2baa9eca8bc500f866ad943b8f63dc99adf.zip | |
hw/intc: Don't clear pending bits on IRQ lowering
According to PLIC specification (chapter 5), there is only one case, when interrupt is claimed. Fix PLIC controller to match this behavior. Signed-off-by: Sergey Makarov <s.makarov@syntacore.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240918140229.124329-3-s.makarov@syntacore.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/sifive_plic.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 8de3a654bc..ed74490dba 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -354,8 +354,10 @@ static void sifive_plic_irq_request(void *opaque, int irq, int level) { SiFivePLICState *s = opaque; - sifive_plic_set_pending(s, irq, level > 0); - sifive_plic_update(s); + if (level > 0) { + sifive_plic_set_pending(s, irq, true); + sifive_plic_update(s); + } } static void sifive_plic_realize(DeviceState *dev, Error **errp) |