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| author | Oran Avraham <oranav@gmail.com> | 2014-06-19 18:06:27 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-06-19 18:33:05 +0100 |
| commit | b6fb3a89e3cd173153f1edc4edbf970987b4ebdd (patch) | |
| tree | 40237715e1bb85cf2c8eec74e01acc7bc7e855d2 /hw/intc | |
| parent | 06955739a283ecaf9e2c7658cd9d471e9967cac4 (diff) | |
| download | focaccia-qemu-b6fb3a89e3cd173153f1edc4edbf970987b4ebdd.tar.gz focaccia-qemu-b6fb3a89e3cd173153f1edc4edbf970987b4ebdd.zip | |
armv7m_nvic: fix AIRCR implementation
The returned reset value was wrong (off by one zero nibble), and qemu didn't log unimplemented writes to the PRIGROUP field. Signed-off-by: Oran Avraham <oranav@gmail.com> Message-id: 1403010447-4627-1-git-send-email-oranav@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/armv7m_nvic.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 75d9c6e41e..1a7af450a7 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -211,7 +211,7 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) cpu = ARM_CPU(current_cpu); return cpu->env.v7m.vecbase; case 0xd0c: /* Application Interrupt/Reset Control. */ - return 0xfa05000; + return 0xfa050000; case 0xd10: /* System Control. */ /* TODO: Implement SLEEPONEXIT. */ return 0; @@ -346,6 +346,9 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) if (value & 5) { qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n"); } + if (value & 0x700) { + qemu_log_mask(LOG_UNIMP, "PRIGROUP unimplemented\n"); + } } break; case 0xd10: /* System Control. */ |