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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-10-18 09:29:43 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-10-18 09:29:44 +0100 |
| commit | e8ddc2eae5ccc41f0815e5c43e70cb04a7e67e2e (patch) | |
| tree | 9c61e0318fe412a4d3f7030b9fdddc2abbb0ad11 /hw/intc | |
| parent | 2d02ac10b6644d71c88cc7943e74d7ad6674fff1 (diff) | |
| parent | 46c032f3afcc05a0123914609f1003906ba63fda (diff) | |
| download | focaccia-qemu-e8ddc2eae5ccc41f0815e5c43e70cb04a7e67e2e.tar.gz focaccia-qemu-e8ddc2eae5ccc41f0815e5c43e70cb04a7e67e2e.zip | |
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging
x86 queue, 2016-10-17 # gpg: Signature made Mon 17 Oct 2016 18:51:07 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-pull-request: (21 commits) target-i386: Don't use cpu->migratable when filtering features target-i386: Return runnability information on query-cpu-definitions target-i386: x86_cpu_load_features() function target-i386: Unset cannot_destroy_with_object_finalize_yet target-i386/kvm: cache the return value of kvm_enable_x2apic() intel_iommu: reject broken EIM intel_iommu: add OnOffAuto intr_eim as "eim" property intel_iommu: redo configuraton check in realize intel_iommu: pass whole remapped addresses to apic apic: add send_msi() to APICCommonClass apic: add global apic_get_class() target-i386: Move warning code outside x86_cpu_filter_features() qmp: Add runnability information to query-cpu-definitions target-i386: xsave: Add FP and SSE bits to x86_ext_save_areas target-i386: Register properties for feature aliases manually target-i386: Remove underscores from feat_names arrays target-i386: Make plus_features/minus_features QOM-based target-i386: Register aliases for feature names with underscores target-i386: Disable VME by default with TCG target-i386: List CPU models using subclass list ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/apic.c | 8 | ||||
| -rw-r--r-- | hw/intc/apic_common.c | 1 |
2 files changed, 7 insertions, 2 deletions
diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 7bd1d279c4..fe15fb6024 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -740,8 +740,10 @@ static uint32_t apic_mem_readl(void *opaque, hwaddr addr) return val; } -static void apic_send_msi(hwaddr addr, uint32_t data) +static void apic_send_msi(MSIMessage *msi) { + uint64_t addr = msi->address; + uint32_t data = msi->data; uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; @@ -762,7 +764,8 @@ static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val) * APIC is connected directly to the CPU. * Mapping them on the global bus happens to work because * MSI registers are reserved in APIC MMIO and vice versa. */ - apic_send_msi(addr, val); + MSIMessage msi = { .address = addr, .data = val }; + apic_send_msi(&msi); return; } @@ -913,6 +916,7 @@ static void apic_class_init(ObjectClass *klass, void *data) k->external_nmi = apic_external_nmi; k->pre_save = apic_pre_save; k->post_load = apic_post_load; + k->send_msi = apic_send_msi; } static const TypeInfo apic_info = { diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 14ac43c186..8d01c9c875 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -18,6 +18,7 @@ * License along with this library; if not, see <http://www.gnu.org/licenses/> */ #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "qapi/error.h" #include "qemu-common.h" #include "cpu.h" |