summary refs log tree commit diff stats
path: root/hw/isa
diff options
context:
space:
mode:
authorBALATON Zoltan <balaton@eik.bme.hu>2021-01-09 21:16:36 +0100
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-02-21 19:42:34 +0100
commit2b98dca9571a1019fcc97694b6220f9301dddd7d (patch)
tree41ae66615e8dd1c9697144a5ef0416051247afd2 /hw/isa
parentc953bf7118261a6af8f306108d5072b5d4efccd0 (diff)
downloadfocaccia-qemu-2b98dca9571a1019fcc97694b6220f9301dddd7d.tar.gz
focaccia-qemu-2b98dca9571a1019fcc97694b6220f9301dddd7d.zip
vt82c686: Reduce indentation by returning early
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMD: Split patch original in 5, this is part 2/5]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'hw/isa')
-rw-r--r--hw/isa/vt82c686.c47
1 files changed, 23 insertions, 24 deletions
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index eebaa0d444..2f69b4d531 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -258,33 +258,32 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
 {
     SuperIOConfig *sc = opaque;
     uint8_t idx = sc->regs[0];
+    bool can_write = true;
 
     if (addr == 0x3f0) { /* config index register */
         idx = data & 0xff;
-    } else {
-        bool can_write = true;
-        /* 0x3f1, config data register */
-        trace_via_superio_write(idx, data & 0xff);
-        switch (idx) {
-        case 0x00 ... 0xdf:
-        case 0xe4:
-        case 0xe5:
-        case 0xe9 ... 0xed:
-        case 0xf3:
-        case 0xf5:
-        case 0xf7:
-        case 0xf9 ... 0xfb:
-        case 0xfd ... 0xff:
-            can_write = false;
-            break;
-        /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
-        default:
-            break;
-
-        }
-        if (can_write) {
-            sc->regs[idx] = data & 0xff;
-        }
+        return;
+    }
+    /* 0x3f1, config data register */
+    trace_via_superio_write(idx, data & 0xff);
+    switch (idx) {
+    case 0x00 ... 0xdf:
+    case 0xe4:
+    case 0xe5:
+    case 0xe9 ... 0xed:
+    case 0xf3:
+    case 0xf5:
+    case 0xf7:
+    case 0xf9 ... 0xfb:
+    case 0xfd ... 0xff:
+        can_write = false;
+        break;
+    /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
+    default:
+        break;
+    }
+    if (can_write) {
+        sc->regs[idx] = data & 0xff;
     }
 }