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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-05-22 19:45:51 -0700 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2018-07-03 00:05:28 +0900 |
| commit | fffde6695f4be3cf484f068f24e894280d7360ea (patch) | |
| tree | a57e84a3446edbaaeea54915d049ffd83a12f400 /hw/lm32/lm32_boards.c | |
| parent | 2acaa2331b96ee92f0df213784f9b6454c3d5edc (diff) | |
| download | focaccia-qemu-fffde6695f4be3cf484f068f24e894280d7360ea.tar.gz focaccia-qemu-fffde6695f4be3cf484f068f24e894280d7360ea.zip | |
target/openrisc: Fix tlb flushing in mtspr
The previous code was confused, avoiding the flush of the old entry if the new entry is invalid. We need to flush the old page if the old entry is valid and the new page if the new entry is valid. This bug was masked by over-flushing elsewhere. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'hw/lm32/lm32_boards.c')
0 files changed, 0 insertions, 0 deletions