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| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-10-14 16:10:42 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2022-11-07 13:12:19 -0500 |
| commit | 23325c8df4318e5f4388dc2e53e6b7c8c3996880 (patch) | |
| tree | c97b6b1cc5e4d451c7bf67a8493a2f6bd789446c /hw/mem | |
| parent | 5fb52f6cc8f621f2e51d181d81401d14e4d45102 (diff) | |
| download | focaccia-qemu-23325c8df4318e5f4388dc2e53e6b7c8c3996880.tar.gz focaccia-qemu-23325c8df4318e5f4388dc2e53e6b7c8c3996880.zip | |
hw/mem/cxl-type3: Add MSIX support
This will be used by several upcoming patch sets so break it out such that it doesn't matter which one lands first. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20221014151045.24781-3-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/mem')
| -rw-r--r-- | hw/mem/cxl_type3.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index a71bf1afeb..568c9d62f5 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -13,6 +13,7 @@ #include "qemu/rcu.h" #include "sysemu/hostmem.h" #include "hw/cxl/cxl.h" +#include "hw/pci/msix.h" /* * Null value of all Fs suggested by IEEE RA guidelines for use of @@ -146,6 +147,8 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) ComponentRegisters *regs = &cxl_cstate->crb; MemoryRegion *mr = ®s->component_registers; uint8_t *pci_conf = pci_dev->config; + unsigned short msix_num = 1; + int i; if (!cxl_setup_memory(ct3d, errp)) { return; @@ -180,6 +183,12 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &ct3d->cxl_dstate.device_registers); + + /* MSI(-X) Initailization */ + msix_init_exclusive_bar(pci_dev, msix_num, 4, NULL); + for (i = 0; i < msix_num; i++) { + msix_vector_use(pci_dev, i); + } } static void ct3_exit(PCIDevice *pci_dev) |